{"id":133192,"date":"2025-01-11T23:19:31","date_gmt":"2025-01-11T17:19:31","guid":{"rendered":"http:\/\/rcl-radio.ru\/?p=133192"},"modified":"2025-01-11T23:20:39","modified_gmt":"2025-01-11T17:20:39","slug":"%d1%82%d0%b8%d0%bf%d1%8b-%d1%80%d0%b5%d0%b3%d0%b8%d1%81%d1%82%d1%80%d0%be%d0%b2-%d0%b2-atmega328","status":"publish","type":"post","link":"http:\/\/rcl-radio.ru\/?p=133192","title":{"rendered":"\u0422\u0438\u043f\u044b \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0432 ATmega328"},"content":{"rendered":"

\u041c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u044b \u0441\u0435\u043c\u0435\u0439\u0441\u0442\u0432\u0430 AVR, \u0442\u0430\u043a\u0438\u0435 \u043a\u0430\u043a ATmega328, \u0441\u043e\u0434\u0435\u0440\u0436\u0430\u0442 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0435 \u0442\u0438\u043f\u044b \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0434\u043b\u044f \u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u044f \u0438 \u0445\u0440\u0430\u043d\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445. \u042d\u0442\u0438 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0438\u0433\u0440\u0430\u044e\u0442 \u043a\u043b\u044e\u0447\u0435\u0432\u0443\u044e \u0440\u043e\u043b\u044c \u0432 \u0440\u0430\u0431\u043e\u0442\u0435 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430, \u043e\u0431\u0435\u0441\u043f\u0435\u0447\u0438\u0432\u0430\u044f \u0432\u0437\u0430\u0438\u043c\u043e\u0434\u0435\u0439\u0441\u0442\u0432\u0438\u0435 \u043c\u0435\u0436\u0434\u0443 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u043c\u0438 \u0435\u0433\u043e \u0447\u0430\u0441\u0442\u044f\u043c\u0438.<\/span><\/p>\n

\u041e\u0441\u043d\u043e\u0432\u043d\u044b\u0435 \u0442\u0438\u043f\u044b \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432:<\/span><\/h1>\n
    \n
  1. \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u043e\u0431\u0449\u0435\u0433\u043e \u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f (General Purpose Registers, GPR)<\/strong><\/span>\n
      \n
    • \u042d\u0442\u043e 32 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 (R0-R31), \u043a\u043e\u0442\u043e\u0440\u044b\u0435 \u043c\u043e\u0433\u0443\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u0432\u0440\u0435\u043c\u0435\u043d\u043d\u043e\u0433\u043e \u0445\u0440\u0430\u043d\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445 \u0438 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044f \u0430\u0440\u0438\u0444\u043c\u0435\u0442\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u043e\u043f\u0435\u0440\u0430\u0446\u0438\u0439. \u041a\u0430\u0436\u0434\u044b\u0439 \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u0438\u043c\u0435\u0435\u0442 \u0440\u0430\u0437\u043c\u0435\u0440 8 \u0431\u0438\u0442.<\/span><\/li>\n
    • \u041e\u043d\u0438 \u0434\u043e\u0441\u0442\u0443\u043f\u043d\u044b \u0447\u0435\u0440\u0435\u0437 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438 \u0440\u0430\u0431\u043e\u0442\u044b \u0441 \u043f\u0430\u043c\u044f\u0442\u044c\u044e \u0438 \u043c\u043e\u0433\u0443\u0442 \u0431\u044b\u0442\u044c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u044b \u0434\u043b\u044f \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0445 \u0446\u0435\u043b\u0435\u0439, \u0442\u0430\u043a\u0438\u0445 \u043a\u0430\u043a \u0445\u0440\u0430\u043d\u0435\u043d\u0438\u0435 \u043f\u0440\u043e\u043c\u0435\u0436\u0443\u0442\u043e\u0447\u043d\u044b\u0445 \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442\u043e\u0432 \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439, \u0443\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u0435\u0439 \u043d\u0430 \u0434\u0430\u043d\u043d\u044b\u0435 \u0438 \u0442.\u0434.<\/span><\/li>\n<\/ul>\n<\/li>\n
    • \u0420\u0435\u0433\u0438\u0441\u0442\u0440 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u044f \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u044b (Status Register, SREG)<\/strong><\/span>\n
        \n
      • \u042d\u0442\u043e\u0442 \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0444\u043b\u0430\u0433\u0438, \u043e\u0442\u0440\u0430\u0436\u0430\u044e\u0449\u0438\u0435 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u043f\u043e\u0441\u043b\u0435 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044f \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0439. \u041d\u0430\u043f\u0440\u0438\u043c\u0435\u0440, \u0444\u043b\u0430\u0433 \u043f\u0435\u0440\u0435\u043d\u043e\u0441\u0430 (C), \u0444\u043b\u0430\u0433 \u043d\u0443\u043b\u044f (Z), \u0444\u043b\u0430\u0433 \u043e\u0442\u0440\u0438\u0446\u0430\u0442\u0435\u043b\u044c\u043d\u043e\u0433\u043e \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442\u0430 (N) \u0438 \u0434\u0440\u0443\u0433\u0438\u0435.<\/span><\/li>\n
      • \u0420\u0435\u0433\u0438\u0441\u0442\u0440 SREG \u0434\u043e\u0441\u0442\u0443\u043f\u0435\u043d \u0442\u043e\u043b\u044c\u043a\u043e \u0434\u043b\u044f \u0447\u0442\u0435\u043d\u0438\u044f\/\u0437\u0430\u043f\u0438\u0441\u0438 \u043f\u043e\u0431\u0438\u0442\u043d\u043e.<\/span><\/li>\n<\/ul>\n<\/li>\n
      • \u0423\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u044c \u0441\u0442\u0435\u043a\u0430 (Stack Pointer, SP)<\/strong><\/span>\n
          \n
        • \u0423\u043a\u0430\u0437\u044b\u0432\u0430\u0435\u0442 \u043d\u0430 \u0432\u0435\u0440\u0448\u0438\u043d\u0443 \u0441\u0442\u0435\u043a\u0430 \u0432 \u043f\u0430\u043c\u044f\u0442\u0438 RAM. \u0418\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u0442\u0441\u044f \u043f\u0440\u0438 \u0432\u044b\u0437\u043e\u0432\u0430\u0445 \u043f\u043e\u0434\u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c \u0438 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439.<\/span><\/li>\n
        • \u0421\u0442\u0435\u043a \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u0442\u0441\u044f \u0434\u043b\u044f \u0441\u043e\u0445\u0440\u0430\u043d\u0435\u043d\u0438\u044f \u0430\u0434\u0440\u0435\u0441\u043e\u0432 \u0432\u043e\u0437\u0432\u0440\u0430\u0442\u0430 \u0438 \u043b\u043e\u043a\u0430\u043b\u044c\u043d\u044b\u0445 \u043f\u0435\u0440\u0435\u043c\u0435\u043d\u043d\u044b\u0445 \u0444\u0443\u043d\u043a\u0446\u0438\u0439.<\/span><\/li>\n<\/ul>\n<\/li>\n
        • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0432\u0432\u043e\u0434\u0430-\u0432\u044b\u0432\u043e\u0434\u0430 (I\/O Registers)<\/strong><\/span>\n
            \n
          • \u0421\u043f\u0435\u0446\u0438\u0430\u043b\u044c\u043d\u044b\u0435 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b, \u043f\u0440\u0435\u0434\u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u043d\u044b\u0435 \u0434\u043b\u044f \u0432\u0437\u0430\u0438\u043c\u043e\u0434\u0435\u0439\u0441\u0442\u0432\u0438\u044f \u0441 \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0439\u043d\u044b\u043c\u0438 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430\u043c\u0438 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430. \u0412 ATmega328 \u0438\u0445 \u0431\u043e\u043b\u0435\u0435 60.<\/span><\/li>\n
          • \u041f\u0440\u0438\u043c\u0435\u0440\u044b: \u043f\u043e\u0440\u0442\u044b \u0432\u0432\u043e\u0434\u0430-\u0432\u044b\u0432\u043e\u0434\u0430 (PORTB, PORTD), \u0442\u0430\u0439\u043c\u0435\u0440\u044b\/\u0441\u0447\u0435\u0442\u0447\u0438\u043a\u0438 (TCCR0A, TCCR1B), UART (UCSR0A, UCSR0B).<\/span><\/li>\n
          • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b I\/O \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u044e\u0442 \u0443\u043f\u0440\u0430\u0432\u043b\u044f\u0442\u044c \u0440\u0430\u0431\u043e\u0442\u043e\u0439 \u043f\u043e\u0440\u0442\u043e\u0432, \u0442\u0430\u0439\u043c\u0435\u0440\u043e\u0432, \u0410\u0426\u041f, USART \u0438 \u0434\u0440\u0443\u0433\u0438\u0445 \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0439\u043d\u044b\u0445 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432.<\/span><\/li>\n<\/ul>\n<\/li>\n
          • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u044c\u043d\u044b\u0445 \u0444\u0443\u043d\u043a\u0446\u0438\u0439 (Special Function Registers, SFR)<\/strong><\/span>\n
              \n
            • \u0412\u043a\u043b\u044e\u0447\u0430\u044e\u0442 \u0432 \u0441\u0435\u0431\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u044f, \u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u044f \u0438 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0445 \u043c\u043e\u0434\u0443\u043b\u0435\u0439 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430.<\/span><\/li>\n
            • \u041f\u0440\u0438\u043c\u0435\u0440: \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u044f \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f\u043c\u0438 (EIMSK, EIFR), \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438 EEPROM (EEARH, EECR).<\/span><\/li>\n<\/ul>\n<\/li>\n
            • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0430\u0434\u0440\u0435\u0441\u0430\u0446\u0438\u0438 (Address Registers)<\/strong><\/span>\n
                \n
              • \u0418\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044e\u0442\u0441\u044f \u0434\u043b\u044f \u0443\u043a\u0430\u0437\u0430\u043d\u0438\u044f \u0430\u0434\u0440\u0435\u0441\u043e\u0432 \u0432 \u043f\u0430\u043c\u044f\u0442\u0438 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c \u0438 \u0434\u0430\u043d\u043d\u044b\u0445.<\/span><\/li>\n
              • \u041d\u0430\u043f\u0440\u0438\u043c\u0435\u0440, \u0440\u0435\u0433\u0438\u0441\u0442\u0440 Z \u2013 \u044d\u0442\u043e 16-\u0431\u0438\u0442\u043d\u044b\u0439 \u0440\u0435\u0433\u0438\u0441\u0442\u0440, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u043c\u043e\u0436\u0435\u0442 \u0443\u043a\u0430\u0437\u044b\u0432\u0430\u0442\u044c \u043d\u0430 \u043b\u044e\u0431\u0443\u044e \u044f\u0447\u0435\u0439\u043a\u0443 \u043f\u0430\u043c\u044f\u0442\u0438 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c \u0438\u043b\u0438 \u0434\u0430\u043d\u043d\u044b\u0445.<\/span><\/li>\n<\/ul>\n<\/li>\n
              • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u044f \u044d\u043d\u0435\u0440\u0433\u043e\u043f\u043e\u0442\u0440\u0435\u0431\u043b\u0435\u043d\u0438\u0435\u043c (Power Management Registers)<\/strong><\/span>\n
                  \n
                • \u041f\u043e\u0437\u0432\u043e\u043b\u044f\u044e\u0442 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u0440\u0435\u0436\u0438\u043c\u044b \u044d\u043d\u0435\u0440\u0433\u043e\u0441\u0431\u0435\u0440\u0435\u0436\u0435\u043d\u0438\u044f \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430.<\/span><\/li>\n
                • \u041f\u0440\u0438\u043c\u0435\u0440: \u0440\u0435\u0433\u0438\u0441\u0442\u0440 SMCR (Sleep Mode Control Register) \u0443\u043f\u0440\u0430\u0432\u043b\u044f\u0435\u0442 \u0441\u043f\u044f\u0449\u0438\u043c\u0438 \u0440\u0435\u0436\u0438\u043c\u0430\u043c\u0438 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430.<\/span><\/li>\n<\/ul>\n<\/li>\n
                • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 (Interrupt Registers)<\/strong><\/span>\n
                    \n
                  • \u0423\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0442 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u043e\u0439 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439. \u041a \u043d\u0438\u043c \u043e\u0442\u043d\u043e\u0441\u044f\u0442\u0441\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u043c\u0430\u0441\u043a\u0438 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 (EIMSK), \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0444\u043b\u0430\u0433\u043e\u0432 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 (EIFR) \u0438 \u0434\u0440\u0443\u0433\u0438\u0435.<\/span><\/li>\n
                  • \u042d\u0442\u0438 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u044f\u044e\u0442, \u043a\u0430\u043a\u0438\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u0440\u0430\u0437\u0440\u0435\u0448\u0435\u043d\u044b, \u0430 \u0442\u0430\u043a\u0436\u0435 \u0445\u0440\u0430\u043d\u044f\u0442 \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044e \u043e \u043f\u0440\u043e\u0438\u0437\u043e\u0448\u0435\u0434\u0448\u0438\u0445 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f\u0445.<\/span><\/li>\n<\/ul>\n<\/li>\n
                  • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b EEPROM<\/strong><\/span>\n
                      \n
                    • \u041c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440 ATmega328 \u0438\u043c\u0435\u0435\u0442 \u0432\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u0443\u044e \u044d\u043d\u0435\u0440\u0433\u043e\u043d\u0435\u0437\u0430\u0432\u0438\u0441\u0438\u043c\u0443\u044e \u043f\u0430\u043c\u044f\u0442\u044c EEPROM, \u0434\u043e\u0441\u0442\u0443\u043f \u043a \u043a\u043e\u0442\u043e\u0440\u043e\u0439 \u043e\u0441\u0443\u0449\u0435\u0441\u0442\u0432\u043b\u044f\u0435\u0442\u0441\u044f \u0447\u0435\u0440\u0435\u0437 \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u044c\u043d\u044b\u0435 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b (\u043d\u0430\u043f\u0440\u0438\u043c\u0435\u0440, EEARL, EEDR).<\/span><\/li>\n<\/ul>\n<\/li>\n
                    • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b A\/D-\u043f\u0440\u0435\u043e\u0431\u0440\u0430\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044f (ADC Registers)<\/strong><\/span>\n
                        \n
                      • \u0423\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0442 \u0430\u043d\u0430\u043b\u043e\u0433\u043e-\u0446\u0438\u0444\u0440\u043e\u0432\u044b\u043c \u043f\u0440\u0435\u043e\u0431\u0440\u0430\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u0435\u043c (\u0410\u0426\u041f). \u041a \u043d\u0438\u043c \u043e\u0442\u043d\u043e\u0441\u044f\u0442\u0441\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b ADCSRA (\u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u0435 \u0438 \u0441\u0442\u0430\u0442\u0443\u0441 \u0410\u0426\u041f), ADMUX (\u0432\u044b\u0431\u043e\u0440 \u043a\u0430\u043d\u0430\u043b\u0430 \u0438 \u0440\u0435\u0436\u0438\u043c\u0430 \u0440\u0430\u0431\u043e\u0442\u044b) \u0438 \u0434\u0440\u0443\u0433\u0438\u0435.<\/span><\/li>\n<\/ul>\n<\/li>\n
                      • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0441\u0442\u043e\u0440\u043e\u0436\u0435\u0432\u043e\u0433\u043e \u0442\u0430\u0439\u043c\u0435\u0440\u0430 (Watchdog Timer Registers)<\/strong><\/span>\n
                          \n
                        • \u041a\u043e\u043d\u0442\u0440\u043e\u043b\u0438\u0440\u0443\u044e\u0442 \u0440\u0430\u0431\u043e\u0442\u0443 \u0441\u0442\u043e\u0440\u043e\u0436\u0435\u0432\u043e\u0433\u043e \u0442\u0430\u0439\u043c\u0435\u0440\u0430, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u043f\u0440\u0435\u0434\u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d \u0434\u043b\u044f \u043f\u0435\u0440\u0435\u0437\u0430\u0433\u0440\u0443\u0437\u043a\u0438 \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u0432 \u0441\u043b\u0443\u0447\u0430\u0435 \u0437\u0430\u0432\u0438\u0441\u0430\u043d\u0438\u044f.<\/span><\/li>\n
                        • \u041f\u0440\u0438\u043c\u0435\u0440: WDTCR (Watchdog Timer Control Register).<\/span><\/li>\n<\/ul>\n<\/li>\n
                        • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b USART<\/strong><\/span>\n
                            \n
                          • \u0423\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0442 \u0443\u043d\u0438\u0432\u0435\u0440\u0441\u0430\u043b\u044c\u043d\u044b\u043c \u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u043c\/\u0430\u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u043c \u043f\u0440\u0438\u0435\u043c\u043d\u0438\u043a\u043e\u043c\/\u043f\u0435\u0440\u0435\u0434\u0430\u0442\u0447\u0438\u043a\u043e\u043c (USART).<\/span><\/li>\n
                          • \u041f\u0440\u0438\u043c\u0435\u0440: UDR (USART Data Register), UBRRH\/L (USART Baud Rate Registers).<\/span><\/li>\n<\/ul>\n<\/li>\n
                          • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b SPI<\/strong><\/span>\n
                              \n
                            • \u0423\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0442 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u043e\u043c SPI (Serial Peripheral Interface).<\/span><\/li>\n
                            • \u041f\u0440\u0438\u043c\u0435\u0440: SPCR (SPI Control Register), SPDR (SPI Data Register).<\/span><\/li>\n<\/ul>\n<\/li>\n
                            • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b TWI (I\u00b2C)<\/strong><\/span>\n
                                \n
                              • \u0423\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0442 \u0434\u0432\u0443\u0445\u043f\u0440\u043e\u0432\u043e\u0434\u043d\u044b\u043c \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u043e\u043c I\u00b2C.<\/span><\/li>\n
                              • \u041f\u0440\u0438\u043c\u0435\u0440: TWBR (TWI Bit Rate Register), TWCR (TWI Control Register).<\/span><\/li>\n<\/ul>\n<\/li>\n
                              • \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0430\u043d\u0430\u043b\u043e\u0433\u043e\u0432\u043e\u0433\u043e \u043a\u043e\u043c\u043f\u0430\u0440\u0430\u0442\u043e\u0440\u0430 (Analog Comparator Registers)<\/strong><\/span>\n
                                  \n
                                • \u0423\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0442 \u0430\u043d\u0430\u043b\u043e\u0433\u043e\u0432\u044b\u043c \u043a\u043e\u043c\u043f\u0430\u0440\u0430\u0442\u043e\u0440\u043e\u043c.<\/span><\/li>\n
                                • \u041f\u0440\u0438\u043c\u0435\u0440: ACSR (Analog Comparator Status and Control Register).<\/span><\/li>\n<\/ul>\n<\/li>\n<\/ol>\n

                                  \u042d\u0442\u0438 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u043e\u0431\u0435\u0441\u043f\u0435\u0447\u0438\u0432\u0430\u044e\u0442 \u0433\u0438\u0431\u043a\u043e\u0441\u0442\u044c \u0438 \u0444\u0443\u043d\u043a\u0446\u0438\u043e\u043d\u0430\u043b\u044c\u043d\u043e\u0441\u0442\u044c \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u043e\u0432 \u0441\u0435\u0440\u0438\u0438 AVR, \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u044f \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0430\u043c \u044d\u0444\u0444\u0435\u043a\u0442\u0438\u0432\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0440\u0435\u0441\u0443\u0440\u0441\u044b \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430 \u0434\u043b\u044f \u0440\u0435\u0448\u0435\u043d\u0438\u044f \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0445 \u0437\u0430\u0434\u0430\u0447.<\/span><\/p>\n

                                  \u0412\u043e\u0442<\/span> \u043d\u0435\u0441\u043a\u043e\u043b\u044c\u043a\u043e<\/span> \u043f\u0440\u0438\u043c\u0435\u0440\u043e\u0432<\/span> \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u044f<\/span> \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432<\/span> \u0432<\/span> \u043a\u043e\u0434\u0435<\/span> \u0434\u043b\u044f<\/span> \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430<\/span> ATmega328<\/span> \r\n\u043d\u0430<\/span> \u044f\u0437\u044b\u043a\u0435<\/span> C<\/span>:<\/span>\r\n\r\n1.<\/span> \u0420\u0430\u0431\u043e\u0442\u0430<\/span> \u0441<\/span> \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430\u043c\u0438<\/span> \u043e\u0431\u0449\u0435\u0433\u043e<\/span> \u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f<\/span>\r\n\r\n#include<\/span> <<\/span>avr<\/span>\/<\/span>io<\/span>.<\/span>h<\/span>><\/span>\r\n\r\nint<\/span> main<\/span>(<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\/\/ \u0418\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u043c \u0440\u0435\u0433\u0438\u0441\u0442\u0440 R16 (\u044d\u0442\u043e \u044d\u043a\u0432\u0438\u0432\u0430\u043b\u0435\u043d\u0442 R16)<\/span>\r\n \u00a0\u00a0\u00a0uint8_t<\/span> a<\/span> =<\/span> 5<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0asm<\/span> volatile<\/span>(<\/span>\"mov r16, %0\"<\/span> :<\/span> :<\/span> \"r\"<\/span>(<\/span>a<\/span>)<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\/\/ \u0412\u044b\u043f\u043e\u043b\u043d\u044f\u0435\u043c \u0441\u043b\u043e\u0436\u0435\u043d\u0438\u0435 \u0441 \u0434\u0440\u0443\u0433\u0438\u043c \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435\u043c<\/span>\r\n \u00a0\u00a0\u00a0uint8_t<\/span> b<\/span> =<\/span> 10<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0asm<\/span> volatile<\/span>(<\/span>\"add r16, %0\"<\/span> :<\/span> :<\/span> \"r\"<\/span>(<\/span>b<\/span>)<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\/\/ \u0421\u0447\u0438\u0442\u044b\u0432\u0430\u0435\u043c \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442 \u043e\u0431\u0440\u0430\u0442\u043d\u043e \u0432 \u043f\u0435\u0440\u0435\u043c\u0435\u043d\u043d\u0443\u044e<\/span>\r\n \u00a0\u00a0\u00a0asm<\/span> volatile<\/span>(<\/span>\"mov %0, r16\"<\/span> :<\/span> \"=r\"<\/span>(<\/span>a<\/span>)<\/span> :<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0while<\/span>(<\/span>1<\/span>)<\/span>;<\/span>\r\n}<\/span>\r\n2.<\/span> \u0423\u0441\u0442\u0430\u043d\u043e\u0432\u043a\u0430<\/span> \u0444\u043b\u0430\u0433\u0430<\/span> \u0432<\/span> \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0435<\/span> \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u044f<\/span> \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u044b<\/span> (<\/span>SREG<\/span>)<\/span>\r\n\r\n#include<\/span> <<\/span>avr<\/span>\/<\/span>io<\/span>.<\/span>h<\/span>><\/span>\r\n\r\nint<\/span> main<\/span>(<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\/\/ \u0423\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u043c \u0444\u043b\u0430\u0433 \u043f\u0435\u0440\u0435\u043d\u043e\u0441\u0430 (C) \u0432 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0435 SREG<\/span>\r\n \u00a0\u00a0\u00a0SREG<\/span> |=<\/span> (<\/span>1<\/span> <<<\/span> C<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0while<\/span>(<\/span>1<\/span>)<\/span>;<\/span>\r\n}<\/span>\r\n3.<\/span> \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430<\/span> \u043f\u043e\u0440\u0442\u0430<\/span> B<\/span> \u0434\u043b\u044f<\/span> \u0432\u044b\u0432\u043e\u0434\u0430<\/span> \u0434\u0430\u043d\u043d\u044b\u0445<\/span>\r\n\r\n#include<\/span> <<\/span>avr<\/span>\/<\/span>io<\/span>.<\/span>h<\/span>><\/span>\r\n\r\nint<\/span> main<\/span>(<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\/\/ \u041d\u0430\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c \u0432\u0441\u0435 \u043f\u0438\u043d\u044b \u043f\u043e\u0440\u0442\u0430 B \u043d\u0430 \u0432\u044b\u0432\u043e\u0434<\/span>\r\n \u00a0\u00a0\u00a0DDRB<\/span> =<\/span> 0xFF<\/span>;<\/span> \/\/ \u0412\u0441\u0435 \u0431\u0438\u0442\u044b \u043f\u043e\u0440\u0442\u0430 B \u043d\u0430\u0441\u0442\u0440\u043e\u0435\u043d\u044b \u043d\u0430 \u0432\u044b\u0445\u043e\u0434<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\/\/ \u0417\u0430\u0434\u0430\u0435\u043c \u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e\u0435 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 \u043d\u0430 \u0432\u044b\u0445\u043e\u0434\u0435<\/span>\r\n \u00a0\u00a0\u00a0PORTB<\/span> =<\/span> 0x00<\/span>;<\/span> \/\/ \u0412\u0441\u0435 \u043f\u0438\u043d\u044b \u043f\u043e\u0440\u0442\u0430 B \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043b\u0435\u043d\u044b \u0432 \u043d\u0438\u0437\u043a\u0438\u0439 \u0443\u0440\u043e\u0432\u0435\u043d\u044c<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0while<\/span>(<\/span>1<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/ \u0418\u043d\u0432\u0435\u0440\u0442\u0438\u0440\u0443\u0435\u043c \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u0432\u0441\u0435\u0445 \u043f\u0438\u043d\u043e\u0432 \u043f\u043e\u0440\u0442\u0430 B<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0PORTB<\/span> ^=<\/span> 0xFF<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/ \u0417\u0430\u0434\u0435\u0440\u0436\u043a\u0430 \u043f\u0435\u0440\u0435\u0434 \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0435\u0439 \u0438\u043d\u0432\u0435\u0440\u0441\u0438\u0435\u0439<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0_delay_ms<\/span>(<\/span>500<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0}<\/span>\r\n}<\/span>\r\n4.<\/span> \u0418\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435<\/span> \u0442\u0430\u0439\u043c\u0435\u0440\u0430<\/span>\/<\/span>\u0441\u0447\u0451\u0442\u0447\u0438\u043a\u0430<\/span> 0<\/span> \u0434\u043b\u044f<\/span> \u0433\u0435\u043d\u0435\u0440\u0430\u0446\u0438\u0438<\/span> \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f<\/span>\r\n\r\n#include<\/span> <<\/span>avr<\/span>\/<\/span>io<\/span>.<\/span>h<\/span>><\/span>\r\n#include<\/span> <<\/span>avr<\/span>\/<\/span>interrupt<\/span>.<\/span>h<\/span>><\/span>\r\n\r\nvolatile<\/span> uint8_t<\/span> count<\/span> =<\/span> 0<\/span>;<\/span>\r\n\r\nISR<\/span>(<\/span>TIMER0_OVF_vect<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0count<\/span>++<\/span>;<\/span>\r\n}<\/span>\r\n\r\nint<\/span> main<\/span>(<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\/\/ \u041d\u0430\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c \u0442\u0430\u0439\u043c\u0435\u0440 0 \u043d\u0430 \u043d\u043e\u0440\u043c\u0430\u043b\u044c\u043d\u044b\u0439 \u0440\u0435\u0436\u0438\u043c \u0440\u0430\u0431\u043e\u0442\u044b<\/span>\r\n \u00a0\u00a0\u00a0TCCR0A<\/span> =<\/span> 0x00<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\/\/ \u0412\u043a\u043b\u044e\u0447\u0430\u0435\u043c \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435 \u043f\u043e \u043f\u0435\u0440\u0435\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044e \u0442\u0430\u0439\u043c\u0435\u0440\u0430 0<\/span>\r\n \u00a0\u00a0\u00a0TIMSK0<\/span> |=<\/span> (<\/span>1<\/span> <<<\/span> TOIE0<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\/\/ \u0417\u0430\u043f\u0443\u0441\u043a\u0430\u0435\u043c \u0442\u0430\u0439\u043c\u0435\u0440 0 \u0441 \u043f\u0440\u0435\u0434\u0434\u0435\u043b\u0438\u0442\u0435\u043b\u0435\u043c 1024<\/span>\r\n \u00a0\u00a0\u00a0TCCR0B<\/span> =<\/span> (<\/span>1<\/span> <<<\/span> CS02<\/span>)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> CS00<\/span>)<\/span>;<\/span> \r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0sei<\/span>(<\/span>)<\/span>;<\/span> \/\/ \u0420\u0430\u0437\u0440\u0435\u0448\u0430\u0435\u043c \u0433\u043b\u043e\u0431\u0430\u043b\u044c\u043d\u044b\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0while<\/span>(<\/span>1<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0if<\/span>(<\/span>count<\/span> >=<\/span> 100<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/ \u0414\u0435\u043b\u0430\u0435\u043c \u0447\u0442\u043e-\u0442\u043e \u043a\u0430\u0436\u0434\u044b\u0435 100 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0count<\/span> =<\/span> 0<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/ \u041d\u0430\u043f\u0440\u0438\u043c\u0435\u0440, \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u043c \u0441\u0432\u0435\u0442\u043e\u0434\u0438\u043e\u0434<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0PORTB<\/span> |=<\/span> (<\/span>1<\/span> <<<\/span> PB0<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0}<\/span>\r\n \u00a0\u00a0\u00a0}<\/span>\r\n}<\/span>\r\n5.<\/span> \u0427\u0442\u0435\u043d\u0438\u0435<\/span> \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f<\/span> \u0441<\/span> \u0430\u043d\u0430\u043b\u043e\u0433\u043e\u0432\u043e\u0433\u043e<\/span> \u0432\u0445\u043e\u0434\u0430<\/span> \u0447\u0435\u0440\u0435\u0437<\/span> ADC<\/span>\r\n\r\n#include<\/span> <<\/span>avr<\/span>\/<\/span>io<\/span>.<\/span>h<\/span>><\/span>\r\n\r\nvoid<\/span> adc_init<\/span>(<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\/\/ \u041d\u0430\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c ADC \u043d\u0430 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435 VCC \u0432 \u043a\u0430\u0447\u0435\u0441\u0442\u0432\u0435 \u043e\u043f\u043e\u0440\u043d\u043e\u0433\u043e \u043d\u0430\u043f\u0440\u044f\u0436\u0435\u043d\u0438\u044f<\/span>\r\n \u00a0\u00a0\u00a0ADMUX<\/span> =<\/span> (<\/span>1<\/span> <<<\/span> REFS0<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\/\/ \u0412\u043a\u043b\u044e\u0447\u0430\u0435\u043c ADC \u0438 \u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u043c \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u044c \u0447\u0430\u0441\u0442\u043e\u0442\u044b \u043d\u0430 128<\/span>\r\n \u00a0\u00a0\u00a0ADCSRA<\/span> =<\/span> (<\/span>1<\/span> <<<\/span> ADEN<\/span>)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> ADPS2<\/span>)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> ADPS1<\/span>)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> ADPS0<\/span>)<\/span>;<\/span>\r\n}<\/span>\r\n\r\nuint16_t<\/span> read_adc<\/span>(<\/span>uint8_t<\/span> channel<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\/\/ \u0412\u044b\u0431\u0438\u0440\u0430\u0435\u043c \u043a\u0430\u043d\u0430\u043b \u0434\u043b\u044f \u043f\u0440\u0435\u043e\u0431\u0440\u0430\u0437\u043e\u0432\u0430\u043d\u0438\u044f<\/span>\r\n \u00a0\u00a0\u00a0ADMUX<\/span> &=<\/span> ~<\/span>(<\/span>(<\/span>1<\/span> <<<\/span> MUX3<\/span>)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> MUX2<\/span>)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> MUX1<\/span>)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> MUX0<\/span>)<\/span>)<\/span>;<\/span> \/\/ \u041e\u0447\u0438\u0441\u0442\u0438\u043c \u0441\u0442\u0430\u0440\u044b\u0435 \r\n                                                                       \/\/ \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0438<\/span>\r\n \u00a0\u00a0\u00a0ADMUX<\/span> |=<\/span> (<\/span>channel<\/span> &<\/span> 0x07<\/span>)<\/span>;<\/span> \/\/ \u0423\u0441\u0442\u0430\u043d\u043e\u0432\u0438\u043c \u043d\u043e\u0432\u044b\u0439 \u043a\u0430\u043d\u0430\u043b<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\/\/ \u041d\u0430\u0447\u0438\u043d\u0430\u0435\u043c \u043f\u0440\u0435\u043e\u0431\u0440\u0430\u0437\u043e\u0432\u0430\u043d\u0438\u0435<\/span>\r\n \u00a0\u00a0\u00a0ADCSRA<\/span> |=<\/span> (<\/span>1<\/span> <<<\/span> ADSC<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\/\/ \u0416\u0434\u0435\u043c \u0437\u0430\u0432\u0435\u0440\u0448\u0435\u043d\u0438\u044f \u043f\u0440\u0435\u043e\u0431\u0440\u0430\u0437\u043e\u0432\u0430\u043d\u0438\u044f<\/span>\r\n \u00a0\u00a0\u00a0while<\/span>(<\/span>ADCSRA<\/span> &<\/span> (<\/span>1<\/span> <<<\/span> ADSC<\/span>)<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0return<\/span> ADC<\/span>;<\/span>\r\n}<\/span>\r\n\r\nint<\/span> main<\/span>(<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0adc_init<\/span>(<\/span>)<\/span>;<\/span>\r\n \u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0while<\/span>(<\/span>1<\/span>)<\/span> {<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0uint16_t<\/span> value<\/span> =<\/span> read_adc<\/span>(<\/span>0<\/span>)<\/span>;<\/span> \/\/ \u0427\u0438\u0442\u0430\u0435\u043c \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 \u0441 \u043a\u0430\u043d\u0430\u043b\u0430 0<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/ \u041e\u0431\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u043c \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u043d\u043e\u0435 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435<\/span>\r\n \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\/\/ ...<\/span>\r\n \u00a0\u00a0\u00a0}<\/span>\r\n}<\/span>\r\n\u042d\u0442\u0438<\/span> \u043f\u0440\u0438\u043c\u0435\u0440\u044b<\/span> \u0434\u0435\u043c\u043e\u043d\u0441\u0442\u0440\u0438\u0440\u0443\u044e\u0442<\/span> \u0431\u0430\u0437\u043e\u0432\u044b\u0435<\/span> \u043e\u043f\u0435\u0440\u0430\u0446\u0438\u0438<\/span> \u0441<\/span> \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430\u043c\u0438<\/span> \u0432<\/span> \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430\u0445<\/span> AVR<\/span>,<\/span> \r\n\u0432\u043a\u043b\u044e\u0447\u0430\u044f<\/span> \u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u0435<\/span> \u0432\u0432\u043e\u0434\u043e\u043c<\/span>-<\/span>\u0432\u044b\u0432\u043e\u0434\u043e\u043c<\/span>,<\/span> \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0443<\/span> \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439<\/span> \u0438<\/span> \u0440\u0430\u0431\u043e\u0442\u0443<\/span> \u0441<\/span> \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0439\u043d\u044b\u043c\u0438<\/span> \u043c\u043e\u0434\u0443\u043b\u044f\u043c\u0438<\/span>.<\/span>\r\n<\/pre>\n","protected":false},"excerpt":{"rendered":"
                                  \u041c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u044b \u0441\u0435\u043c\u0435\u0439\u0441\u0442\u0432\u0430 AVR, \u0442\u0430\u043a\u0438\u0435 \u043a\u0430\u043a ATmega328, \u0441\u043e\u0434\u0435\u0440\u0436\u0430\u0442 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0435 \u0442\u0438\u043f\u044b \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0434\u043b\u044f \u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u044f \u0438 \u0445\u0440\u0430\u043d\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445. \u042d\u0442\u0438 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0438\u0433\u0440\u0430\u044e\u0442 \u043a\u043b\u044e\u0447\u0435\u0432\u0443\u044e \u0440\u043e\u043b\u044c \u0432 \u0440\u0430\u0431\u043e\u0442\u0435 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430, \u043e\u0431\u0435\u0441\u043f\u0435\u0447\u0438\u0432\u0430\u044f \u0432\u0437\u0430\u0438\u043c\u043e\u0434\u0435\u0439\u0441\u0442\u0432\u0438\u0435 \u043c\u0435\u0436\u0434\u0443 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u043c\u0438 \u0435\u0433\u043e \u0447\u0430\u0441\u0442\u044f\u043c\u0438. \u041e\u0441\u043d\u043e\u0432\u043d\u044b\u0435 \u0442\u0438\u043f\u044b \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432: \u0420\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u043e\u0431\u0449\u0435\u0433\u043e \u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f (General Purpose Registers, GPR) \u042d\u0442\u043e 32 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 (R0-R31), \u043a\u043e\u0442\u043e\u0440\u044b\u0435 \u043c\u043e\u0433\u0443\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0434\u043b\u044f \u0432\u0440\u0435\u043c\u0435\u043d\u043d\u043e\u0433\u043e \u0445\u0440\u0430\u043d\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445 \u0438 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044f \u0430\u0440\u0438\u0444\u043c\u0435\u0442\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u043e\u043f\u0435\u0440\u0430\u0446\u0438\u0439. \u041a\u0430\u0436\u0434\u044b\u0439 […]<\/p>\n","protected":false},"author":1,"featured_media":133193,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[285],"tags":[],"class_list":["post-133192","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-atmega328-arduino-ide"],"views":1639,"_links":{"self":[{"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=\/wp\/v2\/posts\/133192","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=133192"}],"version-history":[{"count":2,"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=\/wp\/v2\/posts\/133192\/revisions"}],"predecessor-version":[{"id":133195,"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=\/wp\/v2\/posts\/133192\/revisions\/133195"}],"wp:featuredmedia":[{"embeddable":true,"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=\/wp\/v2\/media\/133193"}],"wp:attachment":[{"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=133192"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=133192"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/rcl-radio.ru\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=133192"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}