{"id":130049,"date":"2023-01-26T22:14:32","date_gmt":"2023-01-26T16:14:32","guid":{"rendered":"http:\/\/rcl-radio.ru\/?p=130049"},"modified":"2023-02-25T17:28:09","modified_gmt":"2023-02-25T11:28:09","slug":"%d1%87%d0%b0%d1%81%d1%82%d0%be%d1%82%d0%be%d0%bc%d0%b5%d1%80-%d0%bd%d0%b0-lgt8f328p-arduino","status":"publish","type":"post","link":"http:\/\/rcl-radio.ru\/?p=130049","title":{"rendered":"\u0427\u0430\u0441\u0442\u043e\u0442\u043e\u043c\u0435\u0440 \u043d\u0430 LGT8F328P (Arduino)"},"content":{"rendered":"

\u041d\u0430 \u0431\u0430\u0437\u0435 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430 LGT8F328P \u043c\u043e\u0436\u043d\u043e \u0441\u0434\u0435\u043b\u0430\u0442\u044c \u0447\u0430\u0441\u0442\u043e\u0442\u043e\u043c\u0435\u0440, \u0441 \u0434\u043e\u0441\u0442\u0430\u0442\u043e\u0447\u043d\u043e \u0431\u043e\u043b\u044c\u0448\u043e\u0439 \u0442\u043e\u0447\u043d\u043e\u0441\u0442\u044c\u044e \u0438 \u0441\u0442\u0430\u0431\u0438\u043b\u044c\u043d\u043e\u0441\u0442\u044c\u044e \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u0438\u0439. \u041f\u043e\u043a\u0430\u0437\u0430\u043d\u0438\u044f \u0447\u0430\u0441\u0442\u043e\u0442\u044b \u0432\u044b\u0432\u043e\u0434\u044f\u0442\u0441\u044f \u043d\u0430 8-\u0438 \u0440\u0430\u0437\u0440\u044f\u0434\u043d\u044b\u0439 \u0441\u0435\u043c\u0438\u0441\u0435\u0433\u043c\u0435\u043d\u0442\u043d\u044b\u0439 \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440 \u043d\u0430 \u0431\u0430\u0437\u0435 \u043c\u0438\u043a\u0440\u043e\u0441\u0445\u0435\u043c\u044b max7219.<\/p>\n

\u041c\u0438\u043a\u0440\u043e\u0441\u0445\u0435\u043c\u0430 MAX7219 \u2013 \u044d\u0442\u043e \u043a\u043e\u043c\u043f\u0430\u043a\u0442\u043d\u044b\u0439 \u0434\u0440\u0430\u0439\u0432\u0435\u0440 \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440\u0430, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0443\u043f\u0440\u0430\u0432\u043b\u044f\u0442\u044c 7-\u0441\u0435\u0433\u043c\u0435\u043d\u0442\u043d\u044b\u043c\u0438 \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440\u0430\u043c\u0438 \u0440\u0430\u0437\u0440\u044f\u0434\u043d\u043e\u0441\u0442\u044c\u044e \u0434\u043e 8 \u0446\u0438\u0444\u0440 \u0438\u043b\u0438 64 \u043e\u0442\u0434\u0435\u043b\u044c\u043d\u044b\u043c\u0438 \u0441\u0432\u0435\u0442\u043e\u0434\u0438\u043e\u0434\u0430\u043c\u0438. \u0414\u0440\u0430\u0439\u0432\u0435\u0440 \u0443\u043f\u0440\u0430\u0432\u043b\u044f\u0435\u0442\u0441\u044f \u043f\u043e \u043f\u043e\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u043e\u043c\u0443 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0443 SPI.<\/p>\n

<\/div>\n

\"\"<\/a><\/p>\n

\u041c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440 LGT8F328P \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 4 \u0442\u0430\u0439\u043c\u0435\u0440\u0430, \u0434\u0432\u0430 \u0438\u0437 \u043a\u043e\u0442\u043e\u0440\u044b\u0445 8-\u0438 \u0440\u0430\u0437\u0440\u044f\u0434\u043d\u044b\u0435 \u0438 \u0434\u0432\u0430 16-\u0438 \u0440\u0430\u0437\u0440\u044f\u0434\u043d\u044b\u0435. \u041d\u0430 \u043e\u0441\u043d\u043e\u0432\u0435 \u0434\u0432\u0443\u0445 16-\u0438 \u0431\u0438\u0442\u043d\u044b\u0439 \u0442\u0430\u0439\u043c\u0435\u0440\u043e\u0432 \u0431\u0443\u0434\u0435\u0442 \u043e\u0441\u0443\u0449\u0435\u0441\u0442\u0432\u043b\u0435\u043d\u043e \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u0438\u0435 \u0447\u0430\u0441\u0442\u043e\u0442\u044b.<\/p>\n

\u0421\u0445\u0435\u043c\u0430 \u0447\u0430\u0441\u0442\u043e\u0442\u043e\u043c\u0435\u0440\u0430 \u043e\u0447\u0435\u043d\u044c \u043f\u0440\u043e\u0441\u0442\u0430\u044f:<\/p>\n

\"\"<\/a><\/p>\n

\u041d\u0430 \u0432\u0445\u043e\u0434 D5 \u043f\u043e\u0434\u0430\u0435\u0442\u0441\u044f \u0441\u0438\u0433\u043d\u0430\u043b \u0443\u0440\u043e\u0432\u043d\u044f TTL, \u0430 \u043d\u0430 \u0432\u044b\u0445\u043e\u0434\u0435 D11 \u043f\u0440\u0438\u0441\u0443\u0442\u0441\u0442\u0432\u0443\u0435\u0442 \u0438\u043c\u043f\u0443\u043b\u044c\u0441\u043d\u044b\u0439 \u0441\u0438\u0433\u043d\u0430\u043b\u0430 (\u043c\u0435\u0430\u043d\u0434\u0440) \u0434\u043b\u044f \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u0440\u0430\u0431\u043e\u0442\u044b \u0447\u0430\u0441\u0442\u043e\u0442\u043e\u043c\u0435\u0440\u0430.<\/p>\n

\u0427\u0430\u0441\u0442\u043e\u0442\u043e\u043c\u0435\u0440 \u0440\u0430\u0431\u043e\u0442\u0430\u0435\u0442 \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c — \u043d\u0430 \u0432\u0445\u043e\u0434 \u04221 Timer_1 \u043f\u043e\u0434\u0430\u0435\u0442\u0441\u044f \u0432\u0445\u043e\u0434\u043d\u043e\u0439 \u0441\u0438\u0433\u043d\u0430\u043b (TTL), Timer_1 \u0441\u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0438\u0440\u043e\u0432\u0430\u043d \u043d\u0430 \u0440\u0430\u0431\u043e\u0442\u0443 \u0441 \u0432\u043d\u0435\u0448\u043d\u0438\u043c \u0442\u0430\u043a\u0442\u043e\u0432\u044b\u043c\u0438 \u0438\u043c\u043f\u0443\u043b\u044c\u0441\u0430\u043c\u0438 \u0438\u0441\u0442\u043e\u0447\u043d\u0438\u043a\u043e\u043c \u043a\u043e\u0442\u043e\u0440\u043e\u0433\u043e \u044f\u0432\u043b\u044f\u0435\u0442\u0441\u044f \u0438\u0437\u043c\u0435\u0440\u044f\u0435\u043c\u044b\u0439 \u0441\u0438\u0433\u043d\u0430\u043b.<\/p>\n

 TCCR1A = 0;TCCR1B = 0;TCNT1=0;\r\n  TCCR1B = (1 << CS12) | (1 << CS11) | (1 << CS10);\r\n  TIMSK1 = (1 << TOIE1);\r\n  TCKCSR = (1 << F2XEN) | (1 << TC2XS1);<\/code><\/pre>\n
\u0411\u0438\u0442\u044b CS12 CS11 CS10 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 TCCR1B \u043d\u0430\u0441\u0442\u0440\u043e\u0435\u043d\u044b \u043d\u0430 \u0432\u043d\u0435\u0448\u043d\u0438\u0439 \u0440\u0435\u0436\u0438\u043c \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f:<\/p>\n
\"\"<\/a><\/p>\n
\u0411\u0438\u0442 TOIE1 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 TIMSK1 \u043f\u0435\u0440\u0435\u0432\u043e\u0434\u0438\u0442 \u0442\u0430\u0439\u043c\u0435\u0440 \u0432 \u0440\u0435\u0436\u0438\u043c — \u0441\u0431\u0440\u043e\u0441 \u043f\u0440\u0438 \u043f\u0435\u0440\u0435\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u0438 (\u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435).<\/p>\n
\u0411\u0438\u0442\u044b F2XEN TC2XS1 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 TCKCSR \u0437\u0430\u043f\u0443\u0441\u043a\u0430\u044e \u0432\u044b\u0441\u043e\u043a\u043e\u0441\u043a\u043e\u0440\u043e\u0441\u0442\u043d\u043e\u0439 \u0440\u0435\u0436\u0438\u043c \u0441\u0438\u043d\u0445\u0440\u043e\u043d\u0438\u0437\u0430\u0446\u0438\u0438.<\/p>\n
\u0415\u0441\u043b\u0438 \u043d\u0430 \u0432\u0445\u043e\u0434 \u04221 \u0442\u0430\u0439\u043c\u0435\u0440\u0430 \u043f\u043e\u0441\u0442\u0443\u043f\u0430\u044e\u0442 \u0442\u0430\u043a\u0442\u043e\u0432\u044b\u0435 \u0438\u043c\u043f\u0443\u043b\u044c\u0441\u044b, \u0441\u0447\u0435\u0442\u0447\u0438\u043a TCNT1 \u043d\u0430\u0447\u0438\u043d\u0430\u0435\u0442 \u043e\u0442\u0441\u0447\u0435\u0442 \u0438\u043c\u043f\u0443\u043b\u044c\u0441\u043e\u0432 \u0434\u043e \u043c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u043e\u0433\u043e \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f 65535 (\u043f\u0440\u0438 \u0443\u0441\u043b\u043e\u0432\u0438\u0438 \u0447\u0442\u043e \u0432\u0445\u043e\u0434\u043d\u043e\u0439 \u0441\u0438\u0433\u043d\u0430\u043b \u0438\u043c\u0435\u0435\u0442 \u0447\u0430\u0441\u0442\u043e\u0442\u0443 \u0432\u044b\u0448\u0435 65535 \u0413\u0446) \u0434\u0430\u043b\u0435\u0435 \u043e\u043d \u043e\u0431\u043d\u0443\u043b\u044f\u0435\u0442\u0441\u044f \u0438 \u043f\u0440\u043e\u0438\u0441\u0445\u043e\u0434\u0438\u0442 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435. \u0412 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u0443\u043a\u0430\u0437\u0430\u043d \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u0439 \u043a\u043e\u0434:<\/p>\n
ISR(TIMER1_OVF_vect) {tic++;}<\/p>\n
\u042d\u0442\u043e\u0442 \u043a\u043e\u0434 \u043f\u0440\u043e\u0441\u0442\u043e \u043f\u043e\u0434\u0441\u0447\u0438\u0442\u044b\u0432\u0430\u0435\u0442 \u043a\u043e\u043b-\u0432\u043e \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439.<\/p>\n
Timer_3 \u0438\u043c\u0435\u0435\u0442 \u0440\u0430\u0437\u0440\u0435\u0448\u0435\u043d\u0438\u0435 16 \u0431\u0438\u0442, \u0435\u0433\u043e \u0437\u0430\u0434\u0430\u0447\u0430 \u0441\u043e\u0441\u0442\u043e\u0438\u0442 \u0432 \u0442\u043e\u0447\u043d\u043e\u043c \u043e\u0442\u0441\u0447\u0435\u0442\u0435 \u0432\u0440\u0435\u043c\u0435\u043d\u0438 \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u0438\u044f \u0432 1 \u0441\u0435\u043a\u0443\u043d\u0434\u0443.<\/p>\n
 TCCR3B = (1 << CS32) | (1 << WGM32);\r\n  TIMSK3 = (1 << OCIE3A);\r\n  OCR3A = CAL;<\/code><\/pre>\n
\u0411\u0438\u0442 CS32 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 TCCR3B \u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u0442 \u043f\u0440\u0435\u0434\u0434\u0435\u043b\u0438\u0442\u0435\u043b\u044c \u043d\u0430 256, \u0431\u0438\u0442 WGM32 \u0430\u043a\u0442\u0438\u0432\u0438\u0440\u0443\u0435\u0442 \u0440\u0435\u0436\u0438\u043c \u0421\u0422\u0421 (\u0441\u0431\u0440\u043e\u0441 \u043f\u0440\u0438 \u0441\u043e\u0432\u043f\u0430\u0434\u0435\u043d\u0438\u0438 \u0441\u0447\u0435\u0442\u043d\u043e\u0433\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 TCNT1 \u0441 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u043c \u0441\u0440\u0430\u0432\u043d\u0435\u043d\u0438\u044f OCR3A).<\/p>\n
\u0420\u0435\u0433\u0438\u0441\u0442\u0440 OCR3A \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 CAL \u043e\u0442\u043c\u0435\u0440\u044f\u044e\u0449\u0435\u0435 1 \u0441\u0435\u043a\u0443\u043d\u0434\u0443.<\/p>\n
\u041f\u0440\u0438 \u0441\u043e\u0432\u043f\u0430\u0434\u0435\u043d\u0438\u0438 \u0441\u0447\u0435\u0442\u043d\u043e\u0433\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 TCNT1 \u0441 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u043c \u0441\u0440\u0430\u0432\u043d\u0435\u043d\u0438\u044f OCR3A \u043f\u0440\u043e\u0438\u0441\u0445\u043e\u0434\u0438\u0442 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435:<\/p>\n
ISR(TIMER3_vect) {\r\n  if (TIFR3 & (1 << OCF3A)){\r\n      TIFR3 = 1 << OCF3A;\r\n      freq = tic*0xFFFF + TCNT1;\r\n      tic=0;TCNT1=0;\r\n      w=1;\r\n  }\r\n}<\/code><\/pre>\n
\u0412 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f Timer_3 \u043f\u0440\u043e\u0438\u0441\u0445\u043e\u0434\u0438\u0442 \u043f\u043e\u0434\u0441\u0447\u0435\u0442 \u0447\u0430\u0441\u0442\u043e\u0442\u044b:<\/p>\n
freq = tic*0xFFFF + TCNT1;<\/code><\/p>\n
\u0442\u043e \u0435\u0441\u0442\u044c \u043a\u043e\u043b-\u0432\u043e \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 Timer_1 \u0443\u043c\u043d\u043e\u0436\u0430\u0435\u0442\u0441\u044f \u043d\u0430 65535, \u0442\u0430\u043a \u043a\u0430\u043a \u043e\u0434\u043d\u043e \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435 \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 65535 \u043e\u0442\u0441\u0447\u0435\u0442\u043e\u0432 \u0441\u0447\u0435\u0442\u043d\u043e\u0433\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 TCNT1 \u0438 \u0434\u0430\u043b\u0435\u0435 \u043a \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u043d\u043e\u043c\u0443 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044e \u043f\u0440\u0438\u0431\u0430\u0432\u043b\u044f\u0435\u0442\u0441\u044f \u043e\u0441\u0442\u0430\u0442\u043e\u043a \u0441\u0447\u0435\u0442\u0430 \u0432 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0435 TCNT1.<\/p>\n
\u041f\u043e\u0441\u043b\u0435 \u0447\u0435\u0433\u043e \u043a\u043e\u043b-\u0432\u043e \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 Timer_1 \u0438 \u043f\u043e\u043a\u0430\u0437\u0430\u043d\u0438\u044f \u0441\u0447\u0435\u0442\u043d\u043e\u0433\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u043e\u0431\u043d\u0443\u043b\u044f\u044e\u0442\u0441\u044f, \u0430 \u0432 \u043f\u0435\u0440\u0435\u043c\u0435\u043d\u043d\u043e\u0439 freq \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442\u0441\u044f \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u043d\u043e\u0439 \u0447\u0430\u0441\u0442\u043e\u0442\u044b, \u043a\u043e\u0442\u043e\u0440\u044b\u0435 \u0432\u044b\u0432\u043e\u0434\u0438\u0442\u0441\u044f \u043d\u0430 \u0432\u043e\u0441\u044c\u043c\u0438 \u0440\u0430\u0437\u0440\u044f\u0434\u043d\u044b\u0439 \u0441\u0435\u043c\u0438\u0441\u0435\u0433\u043c\u0435\u043d\u0442\u043d\u044b\u0439 \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440.<\/p>\n
#define DIN PD4<\/span>\r\n#define CLK PD2<\/span>\r\n#define CS  PD3<\/span>\r\n#define CAL 62502; \/\/62499 = 1 sec <\/span>\r\n\u00a0\r\nstatic<\/span> unsigned long tic,freq;\r\nbool w=1<\/span>;\r\nbyte fq[<\/span>8<\/span>]<\/span>,pd,x;\r\n\u00a0\r\nvoid<\/span> setup(<\/span>)<\/span>{<\/span>\r\n  PORTD |<\/span>= (<\/span>1<\/span> <<<\/span> PD5)<\/span>; \/\/ \u043f\u043e\u0434\u0442\u044f\u0433\u0438\u0432\u0430\u044e\u0449\u0438\u0439 \u0440\u0435\u0437\u0438\u0441\u0442\u043e\u0440 \u043d\u0430 PD5 (\u0432\u0445\u043e\u0434 T1)<\/span>\r\n  DDRB |<\/span>= (<\/span>1<\/span> <<<\/span> PB3)<\/span>; \/\/ D11 OUTPUT 8 MHz<\/span>\r\n  _delay_ms(<\/span>2<\/span>)<\/span>;\r\n  DDRD |<\/span>= (<\/span>1<\/span> <<<\/span> DIN)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> CS)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> CLK)<\/span>;\r\n  PORTD |<\/span>= (<\/span>1<\/span> <<<\/span> CS)<\/span>;\r\n  WriteBit16(<\/span>0x0F, 0<\/span>)<\/span>;\/\/ \u0442\u0435\u0441\u0442 \u0432\u044b\u043a\u043b.<\/span>\r\n  WriteBit16(<\/span>0x0C, 1<\/span>)<\/span>;\/\/ \u0432\u043a\u043b. \u0438\u043d\u0434\u0438\u043a.<\/span>\r\n  WriteBit16(<\/span>0x0A, 0<\/span>)<\/span>;\/\/ \u044f\u0440\u043a\u043e\u0441\u0442\u044c<\/span>\r\n  WriteBit16(<\/span>0x09, 0xFF)<\/span>;\/\/ \u0434\u0435\u0448\u0438\u0444\u0440\u0430\u0442\u043e\u0440\u044b \u0432\u043a\u043b.<\/span>\r\n  WriteBit16(<\/span>0x0B, 7<\/span>)<\/span>;\/\/ \u043a\u043e\u043b-\u0432\u043e \u0440\u0430\u0437\u0440\u044f\u0434\u043e\u0432<\/span>\r\n  cl(<\/span>)<\/span>;\r\n  _delay_ms(<\/span>2<\/span>)<\/span>;\r\n  noInterrupts(<\/span>)<\/span>;\r\n\/\/ TIMER_1 INPUT T1<\/span>\r\n  TCCR1A = 0<\/span>;TCCR1B = 0<\/span>;TCNT1=0<\/span>;\r\n  TCCR1B = (<\/span>1<\/span> <<<\/span> CS12)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> CS11)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> CS10)<\/span>;\r\n  TIMSK1 = (<\/span>1<\/span> <<<\/span> TOIE1)<\/span>;\r\n  TCKCSR = (<\/span>1<\/span> <<<\/span> F2XEN)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> TC2XS1)<\/span>;\r\n\/\/ TIMER_3 1 SEC<\/span>\r\n  TCCR3A = 0<\/span>;\r\n  TCCR3B = 0<\/span>;\r\n  TCNT3=0<\/span>;\r\n  TCCR3B = (<\/span>1<\/span> <<<\/span> CS32)<\/span> |<\/span> (<\/span>1<\/span> <<<\/span> WGM32)<\/span>;\r\n  TIMSK3 = (<\/span>1<\/span> <<<\/span> OCIE3A)<\/span>;\r\n  OCR3A = CAL;\r\n\/\/ TIMER_2 OUTPUT 8 MHz<\/span>\r\nTCCR2A = 0<\/span>;TCCR2B = 0<\/span>;TCNT2=0<\/span>;\r\n  TCCR2A = 1<\/span> <<<\/span> COM2A0 |<\/span>1<\/span> <<<\/span> WGM21;\r\n  TCCR2B = 1<\/span> <<<\/span> CS20;\r\n  OCR2A = 0<\/span>;\r\n  interrupts(<\/span>)<\/span>;\r\n}<\/span>\r\n\u00a0\r\nvoid<\/span> loop(<\/span>)<\/span>{<\/span>\r\n if<\/span>(<\/span>w==1<\/span>)<\/span>{<\/span>w=0<\/span>;\r\n  if<\/span>(<\/span>freq><\/span>=10000000<\/span>)<\/span>{<\/span>WriteBit16(<\/span>0x0B, 7<\/span>)<\/span>;x=8<\/span>;}<\/span>\r\n  if<\/span>(<\/span>freq<<\/span>10000000<\/span>&&<\/span>freq><\/span>=1000000<\/span>)<\/span>{<\/span>WriteBit16(<\/span>0x0B, 6<\/span>)<\/span>;x=7<\/span>;}<\/span>\r\n  if<\/span>(<\/span>freq<<\/span>1000000<\/span>&&<\/span>freq><\/span>=100000<\/span>)<\/span>{<\/span>WriteBit16(<\/span>0x0B, 5<\/span>)<\/span>;x=6<\/span>;}<\/span>\r\n  if<\/span>(<\/span>freq<<\/span>100000<\/span>&&<\/span>freq><\/span>=10000<\/span>)<\/span>{<\/span>WriteBit16(<\/span>0x0B, 4<\/span>)<\/span>;x=5<\/span>;}<\/span>\r\n  if<\/span>(<\/span>freq<<\/span>10000<\/span>&&<\/span>freq><\/span>=1000<\/span>)<\/span>{<\/span>WriteBit16(<\/span>0x0B, 3<\/span>)<\/span>;x=4<\/span>;}<\/span>\r\n  if<\/span>(<\/span>freq<<\/span>1000<\/span>&&<\/span>freq><\/span>=100<\/span>)<\/span>{<\/span>WriteBit16(<\/span>0x0B, 2<\/span>)<\/span>;x=3<\/span>;}<\/span>\r\n  if<\/span>(<\/span>freq<<\/span>100<\/span>&&<\/span>freq><\/span>=10<\/span>)<\/span>{<\/span>WriteBit16(<\/span>0x0B, 1<\/span>)<\/span>;x=2<\/span>;}<\/span>\r\n  if<\/span>(<\/span>freq<<\/span>10<\/span>)<\/span>{<\/span>WriteBit16(<\/span>0x0B, 0<\/span>)<\/span>;x=1<\/span>;}<\/span>\r\n\u00a0\r\n  fq[<\/span>7<\/span>]<\/span>= freq\/<\/span>10000000<\/span>%<\/span>10;\r\n  fq[<\/span>6<\/span>]<\/span>= freq\/<\/span>1000000<\/span>%<\/span>10|<\/span>0b10000000;\r\n  fq[<\/span>5<\/span>]<\/span>= freq\/<\/span>100000<\/span>%<\/span>10;\r\n  fq[<\/span>4<\/span>]<\/span>= freq\/<\/span>10000<\/span>%<\/span>10;\r\n  fq[<\/span>3<\/span>]<\/span>= freq\/<\/span>1000<\/span>%<\/span>10|<\/span>0b10000000;\r\n  fq[<\/span>2<\/span>]<\/span>= freq\/<\/span>100<\/span>%<\/span>10;\r\n  fq[<\/span>1<\/span>]<\/span>= freq\/<\/span>10<\/span>%<\/span>10;\r\n  fq[<\/span>0<\/span>]<\/span>= freq%<\/span>10%<\/span>10;\r\n\u00a0\r\n  for<\/span>(<\/span>int<\/span> i=0<\/span>;i<<\/span>8<\/span>;i++)<\/span>{<\/span>WriteBit16(<\/span>i+1<\/span>, fq[<\/span>i]<\/span>)<\/span>;}<\/span>\r\n  }<\/span>\r\n}<\/span>\r\n\u00a0\r\nISR(<\/span>TIMER1_OVF_vect)<\/span> {<\/span>tic++;}<\/span>\r\n\u00a0\r\nISR(<\/span>TIMER3_vect)<\/span> {<\/span>\r\n  if<\/span> (<\/span>TIFR3 &<\/span> (<\/span>1<\/span> <<<\/span> OCF3A)<\/span>)<\/span>{<\/span>\r\n      TIFR3 = 1<\/span> <<<\/span> OCF3A;\r\n      freq = tic*<\/span>0xFFFF + TCNT1;\r\n      tic=0<\/span>;TCNT1=0<\/span>;\r\n      w=1<\/span>;\r\n  }<\/span>\r\n}<\/span>\r\nvoid<\/span> cl(<\/span>)<\/span>{<\/span>for<\/span>(<\/span>char i=1<\/span>;i<<\/span>=8<\/span>;i++)<\/span>{<\/span>WriteBit16(<\/span>i, 0<\/span>)<\/span>;}<\/span>}<\/span>\r\nvoid<\/span> WriteBit16(<\/span>byte reg, byte data<\/span>)<\/span>{<\/span>  \r\n     PORTD &<\/span>= ~(<\/span>1<\/span> <<<\/span> CLK)<\/span>;PORTD &<\/span>= ~(<\/span>1<\/span> <<<\/span> CS)<\/span>;\r\n     for<\/span>(<\/span>int<\/span> i = 7<\/span>; i ><\/span>= 0<\/span>; i--)<\/span>{<\/span>\r\n        if<\/span>(<\/span>(<\/span>(<\/span>reg >><\/span> i)<\/span> &<\/span> 1<\/span>)<\/span> == 1<\/span>)<\/span>{<\/span>PORTD |<\/span>= (<\/span>1<\/span> <<<\/span> DIN)<\/span>;}<\/span>else<\/span>{<\/span>PORTD &<\/span>= ~(<\/span>1<\/span> <<<\/span> DIN)<\/span>;}<\/span>\r\n        PORTD |<\/span>=(<\/span>1<\/span> <<<\/span> CLK)<\/span>;PORTD &<\/span>= ~(<\/span>1<\/span> <<<\/span> CLK)<\/span>;\r\n        }<\/span>\r\n     for<\/span>(<\/span>int<\/span> i = 7<\/span>; i ><\/span>= 0<\/span>; i--)<\/span>{<\/span>\r\n        if<\/span>(<\/span>(<\/span>(<\/span>data<\/span> >><\/span> i)<\/span> &<\/span> 1<\/span>)<\/span> == 1<\/span>)<\/span>{<\/span>PORTD |<\/span>= (<\/span>1<\/span> <<<\/span> DIN)<\/span>;}<\/span>else<\/span>{<\/span>PORTD &<\/span>= ~(<\/span>1<\/span> <<<\/span> DIN)<\/span>;}<\/span>\r\n        PORTD |<\/span>=(<\/span>1<\/span> <<<\/span> CLK)<\/span>;PORTD &<\/span>= ~(<\/span>1<\/span> <<<\/span> CLK)<\/span>;\r\n        }<\/span>\r\n     PORTD &<\/span>= ~(<\/span>1<\/span> <<<\/span> CLK)<\/span>;PORTD &<\/span>= ~(<\/span>1<\/span> <<<\/span> DIN)<\/span>;PORTD |<\/span>=(<\/span>1<\/span> <<<\/span> CS)<\/span>;\r\n  }<\/span><\/pre>\n
\u041f\u0440\u0438 \u043d\u0430\u043b\u0438\u0447\u0438\u0438 \u043e\u0447\u0435\u043d\u044c \u0442\u043e\u0447\u043d\u043e\u0433\u043e \u0438\u043c\u043f\u0443\u043b\u044c\u0441\u043d\u043e\u0433\u043e \u0433\u0435\u043d\u0435\u0440\u0430\u0442\u043e\u0440\u0430 \u043c\u043e\u0436\u043d\u043e \u043e\u0442\u043a\u0430\u043b\u0438\u0431\u0440\u043e\u0432\u0430\u0442\u044c \u0447\u0430\u0441\u0442\u043e\u0442\u043e\u043c\u0435\u0440 \u043f\u0440\u0438 \u043f\u043e\u043c\u043e\u0449\u0438 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f \u0441\u0447\u0435\u0442\u043d\u043e\u0433\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430:<\/p>\n
#define CAL 62502; \/\/62499 = 1 sec <\/span><\/p>\n
\"\"<\/a><\/p>\n
\u0422\u0430\u043a \u0436\u0435 \u043f\u0440\u0438 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0438 \u043f\u043b\u0430\u0442\u044b \u0432 Arduino IDE \u0440\u0443\u043a\u043e\u0432\u043e\u0434\u0441\u0442\u0432\u0443\u0439\u0442\u0435\u0441\u044c \u044d\u0442\u0438\u043c \u0441\u043a\u0440\u0438\u043d\u0448\u043e\u0442\u043e\u043c:<\/p>\n
\"\"<\/a><\/p>\n
\u0424\u043e\u0440\u0443\u043c — http:\/\/forum.rcl-radio.ru\/viewtopic.php?id=535<\/a><\/p>\n
\"\"<\/a> \"\"<\/a> \"\"<\/a> \"\"<\/a> \"\"<\/a> \"\"<\/a> \"\"<\/a><\/p>\n
\"\"<\/a><\/p>\n
\u041c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u0430\u044f \u0447\u0430\u0441\u0442\u043e\u0442\u0430 \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u0438\u044f \u043c\u043d\u0435 \u043d\u0435 \u0438\u0437\u0432\u0435\u0441\u0442\u043d\u0430, \u0442\u0430\u043a \u043d\u0435\u0442 \u0432 \u043d\u0430\u043b\u0438\u0447\u0438\u0438 \u0433\u0435\u043d\u0435\u0440\u0430\u0442\u043e\u0440\u0430 \u0441 \u0432\u044b\u0445\u043e\u0434\u043d\u043e\u0439 \u0447\u0430\u0441\u0442\u043e\u0442\u043e\u0439 \u0431\u043e\u043b\u0435\u0435 10 \u041c\u0413\u0446.<\/p>\n
\"\"<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"
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